3-2 CPU Design Strategies: RISC vs. CISC

One of the questions that must be addressed by a system architect concerns the number and type of instructions to be included in a specific computer system. One strategy is to include a large number of instruction types and addressing modes. A system of this type is called a complex instruction set computer (CISC). An alternative method is to reduce the complexity of the instruction set, and hence to reduce the logic required for the implementation of the system, including only the instructions needed for the desired application. A system of this type is called a reduced instruction set computer (RISC). In this section, we will examine some of the issues involved in the decision process, and some of the techniques that have evolved with the RISC machines.

The earliest machines were very simple in their architecture and implementation, both because experience with computing systems was nonexistent and because the technology of implementation mandated a simple machine. Thus, the language of the machine was correspondingly simple. However, users of the computers wanted to solve relatively complex problems, and these users described their problems in a language that treated variables and arithmetic at a higher level than the language of the machine. This resulted in what has become known as the semantic gap, which is the gap between the language of the machine and the language of the user. The languages of users (FORTRAN, Pascal, LISP, C. etc.) became more complex to represent increasingly more complex problems. In response to this trend, computers themselves became more complex, changing with the available technology and user demands for speed and versatility. The attempt was to reduce the semantic gap by creating more complex computing systems. This would enable users of computers to more effectively utilize the computational capabilities of the system.

Effective utilization of a computing system is accomplished by creating a suitable bridge for the semantic gap. The most common bridge is a compiler, which accepts as input a problem written in the language of a user, and creates as output a corresponding solution in the language of the machine. Complex instruction set computers seek to reduce the difficulty of the task of the compiler by making the instructions of the machine more closely conform to the instructions of the higher level language.[1]Some systems have been created in which a high level language is the native language of the processor, but this is not a general practice.

Observations of the behavior of programs executing on real machines provided some interesting insight into the operation of computers. These observations indicated that most of the time the computer was utilizing a small subset of all available instructions. Carrying this observation to the next logical step, system architects concluded that the system speed could be enhanced by including only the often used instructions, and by making them as fast as possible. This simplification of the instruction set and the implementation hardware results in a unit that can run faster. However, the more complex functions of a programming language must be accomplished with subroutines or with longer instruction sequences than corresponding CISC instruction sequences.[2] The result is that a program may require more instructions to complete on a RISC machine than on a CISC machine, but the RISC instructions will, in general, have a higher execution rate.

The RISC approach, then, is to create a system that is simpler in architecture and faster in implementation than a CISC machine. With the simplicity comes the promise of speed, and with many implementations this promise is realized. However, care must be taken when comparing machines based on a rate of instructions per second, since the work accomplished by a RISC instruction will, in general, not be as great as the work accomplished by a CISC instruction.

The basic issue, which is treated differently by the RISC and CISC approaches, is one of resource utilization. How can the system resources be used most effectively? Different answers to this question are possible, based on the relative costs associated with the resources by the system architect.

The tenets of RISC architectures strive to maximize the speed and minimize the complexity of the implementation. Simplicity is the basis of both the architectural definition and the implementations. Some of the basic policies which are the result of this type of an architecture are a minimal number of instructions and addressing modes, fixed instruction formats, hardwired instruction decoding, single cycle execution of most instructions, and the use of a load/store type of organization.

Minimal number of instructions and addressing modes. By including only the instructions that are executed often, the system need not include seldom used features. The result is a smaller，faster system, that is capable of doing more instructions in a given amount of time than a CISC machine.

Fixed instruction formats. By restricting the format of the instructions, the tasks of the control system are simplified. In the fetch-decode-execute mechanism of stored program computers, the decode function must identify the work to be done. By causing all of the instructions to use the same format, then the decisions required of a decoder are minimized.

Hardwired instruction decoding. Hardwired logic has traditionally been faster than memory based techniques, such as microcode. The speed ratio of data memory and microcode memory has been steadily decreasing in recent years, so the use of microcode for speed is not as beneficial now as it was previously, although the use of microcode for versatility is still attractive. Thus, to enhance the speed of the control function, hardwired logic for instruction decode is a reasonable alternative.

Single cycle execution of instructions. If a computer system can be so organized that one instruction is executed in each cycle, then by some standards maximum utilization of all system resources can be approached. However, this limits some of the action of a system, since certain types of operations cannot be accomplished in a single cycle. Some RISC systems deviate from this to allow certain instructions to take two (or more) cycles, which permits reuse of certain system resources, or allows for delays through logic that require more time than allowed in a single cycle.

Load/store memory organization. With a load/store memory system, the only instructions that deal with memory are those that load information into registers from memory or that store information from registers to memory. All arithmetic/logic instructions work with values in registers. With this organization, the operands are readily available, and can be extracted as needed from the registers. The RISC technique relies on the observation that in general information will be used several times before results are written to memory. The CISC technique, which does not restrict the location of the operands for the instructions, allows either the register intensive technique or memory-to-memory operations to be used.

In addition to the tenets listed above, the RISC architectures rely on effective utilization of additional architectural techniques such as pipelining, multiple data paths, and large register sets. These techniques are not strictly associated with RISC machines, but combining the techniques with the reduced instruction set ideas often results in a higher speed system. At this point we should hasten to add that not all RISC systems adhere to all of the tenets listed above, and that most available RISC systems violate at least one of them.

WORDS AND PHRASES

architect  设计师

deviate   背离,偏离

extract   取出

hardwired硬件实现的

hasten    促进

intensive   集中的,加强的

mandate   托管

maximize    把.....增加到最大程度

minimize   把.....减小到最小程度

microcode     微码

pipelining     流水线法

semantic     语义的

subset    子集

subroutine    子程序

tenet     宗旨,原则

violate   违反

devoid of 缺乏,没有

in terms of按照, 以……来(表示)

sort out整理,拣出

strive to争取,努力

NOTES

[1] Complex instruction set computers seek to reduce the difficulty of the task of the compiler by making the instructions of the machine more closely conform to the instructions of the higher level language.

复杂指令集计算机采用使机器的指令更接近高级语言指令的方式以寻求降低编译器任务的复杂度。

[2] However, the more complex functions of a programming language must be accomplished with subroutines or with longer instruction sequences than corresponding CISC instruction sequences.

然而，（在RISC机器中）某种编程语言更复杂功能的实现必须用子程序或比对应的CISC机器指令序列更长的指令序列来完成。