2-3 The Future of Configurable Computing

Configurable computing is still an extremely young field. Although Gerald Estrin of the University of California at Los Angeles proposed configurable computing in the late 1960s, the first demonstrations did not occur until a few years ago, and current FPGAs, with up to 100,000 logic elements, still do not come close to exploiting the full possibilities of the technique. Future FPGAs will be much larger; as with many other integrated circuits, the number of elements on a single FPGA has doubled roughly every 18 months. Before the decade is out, we expect to see FPGAs that have a million logic elements. Such chips will have much broader application, including highly complex communications and signal-processing algorithms.

Academic researchers and manufacturers are overcoming numerous other design limitations that have hindered the adoption of configurable computing. Not all computations can be implemented efficiently with today's FPGAs: they are well suited to algorithms composed of bit-level operations, such as pattern matching and integer arithmetic, but they are ill suited to numeric operations, such as high-precision multiplication or floating-point calculations. Dedicated multiplier circuits such as those used in microprocessor and digital signal chips can be optimized to perform more efficiently than multiplier circuits constructed from configurable logic blocks in an FPGA.[1]  Furthermore, FPGAs currently provide very little on-chip memory for storage of intermediate results in computations; thus, many configurable computing applications require large external memories. The transfer of data to and from the FPGA increases power consumption and may slow down the computations.

Fortunately, researchers are developing advanced FPGAs that contain memory, arithmetic processing units and other special-purpose blocks of circuitry. Andre DeHon and Thomas F. Knight, Jr., of the Massachusetts Institute of Technology have proposed an FPGA that stores multiple configurations in a series of memory banks. In a single clock cycle, which is on the order of tens or hundreds of nanoseconds, the chip could swap one configuration for another configuration without erasing partially processed data.

Meanwhile Brad L. Hutchings of Brigham Young University has used configurable computing to build a dynamic instruction set computer (DISC), which effectively marries a microprocessor to an FPGA and demonstrates the potential of automatic reconfiguration using stored configurations. As a program runs, the FPGA requests reconfiguration if the designated circuit is not resident. DISC allows a designer to create and store a large number of circuit configurations and activate them much as a programmer would initiate a call to a software subroutine in a microprocessor.

The Colt Group, led by Peter M. Athanas of Virginia Polytechnic Institute and State University, is investigating a run-time reconfiguration technique called Wormhole that lends itself to distributed computing. The unit of computing is a stream of data that creates custom logic as it moves through the reconfigurable hardware.

John Wawrzynek and his colleagues at the University of California at Berkeley are developing systems that combine a microprocessor and an FPGA. Special compiler software would take ordinary program code and automatically generate a combination of machine instructions and FPGA configurations for the fastest overall performance. This approach takes advantage of opportunities to integrate a processor and an FPGA on a single chip.

FPGAs will never replace microprocessors for general-purpose computing tasks, but the concept of configurable computing is likely to play a growing role in the development of high-performance computing systems. The computing power that FPGAs offer will make them the devices of choice for applications involving algorithms in which rapid adaptation to the input is required.

In addition, the line between programmable processors and FPGAs will become less distinct: future generations of FPGAs will include functions such as increased local memory and dedicated multipliers that are standard features of today's microprocessors; there are also next-generation microprocessors under development whose hardware supports limited amounts of FPGA-like reconfiguration. Indeed, just as computers connected to the Internet can now automatically download special-purpose software components to perform particular tasks, future machines might download new hardware configurations as they are needed.[2] Computing devices 10 years from now will include a strong mix of software-programmable hardware and hardware-configurable logic. 

WORDS AND PHRASES

bank(数据)库，银行

erase [I’reiz]抹去，擦掉，消磁

DISC（dynamic instruction set computer）动态指令集计算机

NOTES

[1] Dedicated multiplier circuits such as those used in microprocessor and digital signal chips can be optimized to perform more efficiently than multiplier circuits constructed from configurable logic blocks in an FPGA.

例如用于微处理器和数字信号处理芯片的专用乘法器电路，在优化后比现场可编程门阵列中可配置逻辑块构成的乘法器电路的运行更加高效。

[2] Indeed, just as computers connected to the Internet can now automatically download special-purpose software components to perform particular tasks, future machines might download new hardware configurations as they are needed.

事实上，正如网络上的计算机可以自动下载专用软件组件来完成特定的任务一样，未来的机器也可以在需要时下载新的硬件配置。