module sinw (clk,data);

input clk;

output[7:0] data;

reg[7:0] data;

reg[5:0] adr;

always @ (posedge clk)

adr=adr+1'b1;

always @(adr)

begin

  case(adr)

6'd0: data=255;

6'd1: data=254;

6'd2: data=252;

6'd3: data=249;

6'd4: data=245;

6'd5: data=239;

6'd6: data=233;

6'd7: data=225;

6'd8: data=217;

6'd9: data=207;

6'd10: data=197;

6'd11: data=186;

6'd12: data=174;

6'd13: data=162;

6'd14: data=150;

6'd15: data=137;

6'd16: data=124;

6'd17: data=114;

6'd18: data=99;

6'd19: data=87;

6'd20: data=75;

6'd21: data=64;

6'd22: data=53;

6'd23: data=43;

6'd24: data=34;

6'd25: data=26;

6'd26: data=19;

6'd27: data=13;

6'd28: data=8;

6'd29: data=4;

6'd30: data=1;

6'd31: data=0;

6'd32: data=0;

6'd33: data=1;

6'd34: data=4;

6'd35: data=8;

6'd36: data=13;

6'd37: data=19;

6'd38: data=26;

6'd39: data=34;

6'd40: data=43;

6'd41: data=53;

6'd42: data=64;

6'd43: data=75;

6'd44: data=87;

6'd45: data=99;

6'd46: data=112;

6'd47: data=124;

6'd48: data=137;

6'd49: data=150;

6'd50: data=162;

6'd51: data=174;

6'd52: data=186;

6'd53: data=197;

6'd54: data=207;

6'd55: data=217;

6'd56: data=225;

6'd57: data=233;

6'd58: data=239;

6'd59: data=245;

6'd60: data=249;

6'd61: data=252;

6'd62: data=254;

6'd63: data=255;

  endcase

end

endmodule