VHDL源码：
ENTITY SN74138 IS
PORT (A,B,C,EN:IN BIT;
Y:OUT BIT_VECTOR(7 DOWNTO 0));
END ENTITY SN74138;
ARCHITECTURE DEMO OF SN74138 IS
SIGNAL ADR:BIT_VECTOR(2 DOWNTO 0);
BEGIN
ADR<=C & B & A;
PROCESS(ADR,EN)
BEGIN
IF EN='0' THEN
Y<=(OTHERS=>'1');
ELSE
CASE ADR IS
WHEN "000"=> Y<="11111110";
WHEN "001"=> Y<="11111101";
WHEN "010"=> Y<="11111011";
WHEN "011"=> Y<="11110111";
WHEN "100"=> Y<="11101111";
WHEN "101"=> Y<="11011111";
WHEN "110"=> Y<="10111111";
WHEN "111"=> Y<="01111111";
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE DEMO;
2. VerilogHDL源码：
module eg321(
input a,b,c,en,
output reg [7:0]y);
reg [2:0]adr;
always @(a,b,c,en)
begin
adr={a,b,c};
if(en==0) y<=8'b00000000;
else
case(adr)
3'b000:y<=8'b11111110;
3'b001:y<=8'b11111101;
3'b010:y<=8'b11111011;
3'b011:y<=8'b11110111;
3'b100:y<=8'b11101111;
3'b101:y<=8'b11011111;
3'b110:y<=8'b10111111;
3'b111:y<=8'b01111111;
default:y<=8'b00000000;
endcase
end
endmodule
